`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:27:52 11/28/2012
// Design Name:   DOWN_SAMPLE_BLOCK
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/downsample_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DOWN_SAMPLE_BLOCK
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module downsample_simu;

	// Inputs
	reg clk;
	reg rst;
	reg [15:0] data_in_r;
	reg [15:0] data_in_i;

	// Outputs
	wire [15:0] data_out_r;
	wire [15:0] data_out_i;
	
	integer i;

	// Instantiate the Unit Under Test (UUT)
	DOWN_SAMPLE_BLOCK uut (
		.clk(clk), 
		.rst(rst), 
		.data_in_r(data_in_r), 
		.data_out_r(data_out_r), 
		.data_in_i(data_in_i), 
		.data_out_i(data_out_i)
	);

	always #10 clk = ~clk;
	
	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		data_in_r = 0;
		data_in_i = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		rst = 1;
        
		// Add stimulus here
		for(i=0;i<50;i=i+1)
			#20 data_in_r = i;
			

	end
      
endmodule

